1. Field of the Invention
The present invention relates to a shallow trench isolation (STI) type semiconductor device and method of forming the same. More particularly, the present invention relates to a STI type semiconductor device and method of forming the same, which can prevent the electric field from concentrating to an edge portion of a substrate in an active region.
2. Description of the Related Art
As the elements incorporated into a semiconductor device are integrated to a high degree, there is a growing tendency to increasingly use an STI method as a method of forming an isolation layer as compared with a local oxidation of silicon (LOCOS) method.
The STI method generally comprises etching a substrate to form trenches for isolation, and filling the trenches with an insulating layer. Thus, each of isolated regions is separated by the trenches and the insulating layer filled therein. However, when the trenches are filled with an oxide layer for insulation and a subsequent thermal process is carried out, the oxygen diffusion sometimes occurs at interfaces or edges of the oxide layer to oxidize corresponding portions of the inner walls of the trenches additionally. At this time, since the volume is increased due to the oxidation, damage such as a dislocation of crystallized structure may occur.
To solve this problem, there is proposed a method of using a silicon nitride liner. An example of that method is disclosed in U.S. Pat. No. 5,747,866 to Ho et al., in which, after the silicon nitride liner is formed on an inner wall of a trench, the trench is filled with a silicon oxide layer. At this time, the silicon nitride liner acts as an oxygen diffusion stop layer to prevent the damage of the substrate due to the oxidation. However, in this case, another problem may be presented, as described below.
FIG. 1 to FIG. 4 illustrate flow diagrams of the process steps of a conventional method of forming an STI type semiconductor device, demonstrating a problem when a silicon nitride liner is formed in an inner wall of a trench.
Referring to FIG. 1, first a pad oxide film 11 is formed on a substrate 10. Then, a silicon nitride layer as an etch protecting layer 13 is deposited on the pad oxide film 11. Thereafter, the etch protecting layer 13 in a trench-intended region is removed by means of a patterning process. The patterning process is carried out through a general photolithography and etching. Continuously, the substrate 10 is etched to form a trench 15 by using the etch protecting layer 13 as a mask.
Referring to FIG. 2, an inner wall oxide film 17 is formed to a thickness of 200 to 300 xc3x85 in an inner wall of the trench 15 by means of a thermal oxidation process. The thermal oxidation process cures damages generated on the inner wall of the trench 15 during the etching process for forming the trench 15. Then, a silicon nitride layer is formed over the whole surface of the substrate 10. Consequently, a liner 19 is formed in the inner wall of the trench 15.
Referring to FIG. 3, a CVD silicon oxide layer 21 is deposited over the substrate 10 over which the liner 19 is formed. As a result, the trench 15 is filled with the CVD silicon oxide layer 21. Then, the portion of the CVD silicon oxide layer 21 formed on the etch protecting layer 13 in an active region is removed by planarization etching.
Referring to FIG. 4, the etch protecting layer 13 covering the active region is wet-etched and removed. At this time, a top end of the liner 19 coming in contact with the etch protecting layer 13 is also removed. Particularly, since the etch protecting layer 13 is over-etched to be completely removed, the top end of the liner 19 is deeply etched below the upper surface of the substrate 10. Consequently, a reduced liner 19xe2x80x2 only remains between the isolation layer and the active region, so that a xe2x80x98dentxe2x80x99 phenomenon of forming a concave space in the place in which the removed top end of the liner 19 was located occurs. This concave space is enlarged in the following cleaning process, when the CVD silicon oxide layer 21 and the inner wall oxide film 17 adjacent thereto are etched by means of a fluoride containing detergent.
When the xe2x80x98dentxe2x80x99 phenomenon occurs, the concave space may be filled with polysilicon in the following process for forming gates. Polysilicon filled in the concave space may result in a gate bridge. Also, it may cause a xe2x80x98humpxe2x80x99 phenomenon of forming parasite transistors, which makes normal transistor elements not form the linear transistor characteristic, and increases of the leakage current.
To prevent the xe2x80x98dentxe2x80x99 phenomenon, various methods have been proposed. Among these methods are, an STI method using a pull back process, which is disclosed in Korean Patent Application No. 98-21,037. According to that Korean Patent Application, after forming a trench as shown on FIG. 1, an etch protecting layer 13 covering an active region is isotropically etched to form a reduced pattern 13xe2x80x2 which exposes a portion of the active region around the trench 15 as shown in FIG. 5. Then, an inner wall of the trench 15 is oxidized to form an inner wall oxide film 17 to a thickness of 150 to 300 xc3x85. Thereafter, a silicon nitride film as a liner 19 is formed. As the liner 19 is formed, the portion of the active region around the trench 15 is almost covered with the liner 19, as shown in FIG. 6.
Next, a CVD silicon oxide layer 21 is deposited over the substrate 10 to fill the trench 15. Then, a portion of the CVD silicon oxide layer 21 formed over the etch protecting layer 13 in an active region is removed by planarization etching. Thereafter, the reduced pattern 13xe2x80x2 is wet-etched. At this time, a top end of the liner 19 covering the portion of the active region around the trench 15 is removed, but a portion of the liner 19 formed on the inner wall of the trench 15 remains, as shown in FIG. 7. Thus, the xe2x80x98dentxe2x80x99 phenomenon of forming the concave space in the vicinity of the top end of the inner wall of the trench 15 can be prevented.
However, in the STI method using the pull back process, a top end of the inner wall of the trench 15, i.e., an edge portion of the upper surface of the substrate in the active region is covered with the liner 19xe2x80x2 and the inner wall oxide film 17, so that when a gate insulating film is formed after removing the etch protecting layer and the pad oxide film 11, oxygen is not supplied thereto very well. Accordingly, an oxide layer forming the gate insulating film is thinly formed on the edge portion of the upper surface of the substrate in the active region in the vicinity of the top end of the inner wall of the trench 15 compared with that on the other portion. This may result in problems of reducing the value of the breakdown charge Qbd to deteriorate the reliability in the insulation, and generating the leakage current.
Also, in other method for preventing the xe2x80x98dentxe2x80x99 phenomenon, an edge portion of the upper surface of the substrate in the active region is also protected very well, so that it comes to have an angled shape while the etching processes for forming trenches are carried out. When the edge portion has an angular shape, the high electric field can be concentrated thereto, thereby resulting in the insulation damage or the current leakage.
It is a feature of an embodiment of the present invention to provide an improved STI type semiconductor device and method of forming the same, which can prevent the xe2x80x98dentxe2x80x99 phenomenon and decrease the degradation in the transistor characteristic resulting from the substrate having an angled shape at an edge portion of the upper surface of a substrate in an active region.
This and other features are provided, according to the present invention, by an STI type semiconductor device comprising at least one trench formed on a silicon substrate to define at least one active region, a silicon thermal-oxide film formed on an inner wall of the trench, and a CVD silicon oxide layer filling the trench on which the silicon thermal-oxide film is formed. An edge portion of the substrate in the active region forming a top end portion of the inner wall of the trench has a radius of curvature more than twice larger than a thickness of a gate oxide layer formed on the edge portion.
Also, the present invention is adapted to apply when a pull back process is used and a liner for an oxygen barrier is formed to be extended to an edge of the substrate in the active region. In the pull back process, a portion of the liner extended up from an upper surface of the substrate forming the active region is mainly removed as an etch protecting pattern and is wet-etched to be completely removed.
The liner for the oxygen barrier is formed of silicon nitrides. When the pull back process is carried out, an etch protecting layer forming the etch protecting pattern is etched to reduce its thickness and width. The reduced width of the etch protecting layer is within the range of 50 to 1,000 xc3x85. Accordingly, the liner is formed to be further enlarged by as much as 50 to 1,000 xc3x85 onto the upper surface of the substrate in the active region. After the etch protecting layer pattern is wet-etched to be removed, a top end of the liner is maintained at the same level as or at a level higher than the upper surface of the substrate. Also, after an over-etching process is carried out to remove a top end of the thermal-oxide film formed on the inner wall of the trench, the top end of the liner is maintained above a level that is located under 150 xc3x85 from the upper surface of the silicon substrate.
According to another aspect of the present invention, there is provided a shallow trench isolation type semiconductor device comprising an isolation layer formed on a silicon substrate to define at least one active region, and a liner for an oxygen diffusion barrier interposed between the isolation layer and the silicon substrate. A horizontal distance from a top end of an inner wall of the liner to a corresponding level position on a plane vertically extended from an edge of an upper surface of the isolation layer is within the range of 300 to 600 xc3x85 and that a line extended from a center of an upper surface of the substrate in the active region to an edge of the upper surface of the substrate in the active region adjacent to the isolation layer has an angle of 15 to 35 degrees to a horizontal plane.
According to another aspect of the present invention, there is provided a method of forming a shallow trench isolation type semiconductor device comprising forming an etch protecting layer pattern defining at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate on which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to the depth of 100 to 350 xc3x85, preferably 200 xc3x85 from the upper surface of the substrate, and forming a gate oxide film on the substrate through which the active region and the top end are exposed.
In a preferred method of the present invention, forming the gate oxide film includes forming a buffer oxide film for ion implantation on the substrate through which the active region and the top end are exposed, removing the buffer oxide film after ion implantation, and forming the gate oxide film on the substrate on which the buffer oxide film is removed, by means of a thermal oxidation process.
Forming the etch protecting layer pattern includes forming a silicon nitride layer or a silicon nitride-oxide layer over the substrate on which a pad oxide film is formed, and patterning it. Therefore, the method of the present invention includes removing the pad oxide film after removing the etch protecting layer pattern. Also, removing the thermal-oxide film is carried out along with removing the pad oxide film.
Alternatively, forming the etch protecting layer pattern can include forming a thin silicon oxide layer as a sacrificial layer before patterning.
As apparent from the foregoing, the present invention is used under the conditions that after the etch protecting layer is removed, the edge portion of the upper surface of the substrate in the active region adjacent to the trench has an angled shape and the thermal-oxide film disposed in the inner wall of the trench is remained above the level which is located below 150 xc3x85 from the upper surface of the substrate. Accordingly, the present invention is adapted to use in a STI type semiconductor device using a pull back process.
Also, the present invention can obtain a good effect when a thickness of the thermal-oxide film disposed in the inner wall of the trench is above about 200 xc3x85. The reason is that when the thermal-oxide film is removed, the edge portion of the substrate in the active region forming the top end of the inner wall of the trench is exposed to a space corresponding to the thickness of the thermal-oxide film. The more the edge portion is exposed, the more it is oxidized when the buffer oxide layer is forming. Also, the more the edge portion of the substrate in the active region is oxidized, the more it becomes rounded or curved. This rounded profile prevents a thickness of the gate insulating film from being thin in the edge portion when it is formed. Also, as the curvature of the edge portion of the substrate in the active region is more rounded, the high electric field can be prevented from being concentrated thereto, thereby reducing the insulation damage.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.